A semiconductor device, typically a NAND flash memory provided with a multiplicity of memory cells are configured by memory cell transistors and peripheral circuit transistors formed on active areas isolated by element isolation regions such as an STI (Shallow Trench Isolation). In the memory cell region where the memory cells are formed, the element isolation region is configured in relatively narrower width, whereas in the peripheral circuit region where the peripheral transistors are formed, the element isolation region is configured in relatively wider width.
In order to form the above configured element isolation region, first, a resist is coated, exposed to light, and developed on the silicon substrate. Then, element isolation trenches are defined by dry etch using a silicon nitride film, or the like, as a mask. The dry etch, typically RIE (Reactive Ion Etching), etches a floating gate, a silicon oxide film (referred to as a tunnel insulating film in the memory cell region and a gate insulating film in the peripheral circuit region), and the silicon substrate in the listed sequence. Then, insulating film such as silicon oxide film is filled in the element isolation trench.
When dry etching the silicon substrate, relatively less amount of silicon is etched in the memory cell region since the opening of the element isolation trenches are narrower in the memory cell region, whereas in the peripheral circuit region, greater amount of silicon is etched since the opening of the element isolation trenches are wider in the peripheral circuit region, thus, resulting in greater tendency of the element isolation trenches in the peripheral circuit region being deeper than those in the memory cell region.
Device integration requires deeper element isolation trenches in the memory cell region to obtain sufficient element isolation, and this results in increasingly deeper element isolation trenches in the peripheral circuit region. When element isolation insulating film comprising silicon oxide film is filled in such element isolation trenches in the memory cell region and the peripheral circuit region, the silicon oxide film filled in the peripheral circuit region becomes greater in volume because of the above described difference in the trench configuration. Especially when employing hard coated polysilazane film as the silicon oxide film, the sizable volume required in the peripheral circuit region caused cracks in the silicon substrate by the stress produced when the polysilazane film is hardened. Such cracks lead to problems such as increase in junction leak current.
When forming a high-concentration impurity region taking an LDD (Lightly Doped Drain) structure in the semiconductor substrate, increased instances of linear defects such as dislocation primarily originating from crystal defects are observed at the depth of pn junction formed by ion implantation, in other words, at the depth where the impurity concentration is at its peak. This leads to further increase in junction leak current. Related field of technology is discussed in publications such as JP 2006-32549 A and JP 2004-228557 A.